Transistor memory system



This invention relates to a circuit arrangement comprising a chain oftransistors in which each transistor, in the presence of free chargestorage in its base zone, determines the free charge storage in the basezone of a succeeding transistor of the chain by means of interrogatingpulses which act as a collector supply voltage. Such a circuitarrangement -is described in co-pending patent specification Serial No.625,726, liled December 3, 1956. The arrangement may be used yforshifting infomation given in binary code, for example in calculatingmachines or in automatic telephony.

The arrangements described in said co-pending patent specificationinvariably require the use of a base separating rectifier in order tomaintain the base at a floating potential during the occurrence of thesaid interrogating pulses. The present invention .provides a circuitarrangement in which these separating rectiiiers can be dispensed with.It is characterized in that the collector of a preceding transistor ofthe chain is connected, through a resistor conducting in bothdirections, to the base of a succeeding transistor, said resistortogether with a resistor included in the collector circuit of thepreceding transistor being sufficiently large to prevent any free chargestorage lof the second transistor from flowing away in the intervalbetween two interrogating pulses supplied to said second transistor.

The invention is based on the recognition that, if a succeedingtransistor is controlled from the collector of a preceding transistor,the values of the resistors used can be made so high that even if thesaid separating rectiiier is omitted (the collector of the precedingtransistor thus being connected to the base of the succeeding transistorthrough a resistor conducting in both directions) the base potential canbe assumed to remain floating.

In order that the invention may readily be carried into etect, oneembodiment thereof will now be described with reference to theaccompanying diagrammatic drawings, in which FIG. l shows a circuitarrangement in accordance with the `invention and FIG. 2 showsvoltage-time diagrams and current-time diagrams illustrating thearrangement shown in FIG. l.

In FIG. l, reference numerals 1, 2, 3, 4, 5, 6 designate a number oftransistors which, in the presence of free charge storage in their basezones, by means of interrogatin-g pulses A, B acting as collector supplyvoltage pass current through corresponding collector resistors 7, 8, 9,10, l1, 12. Erasing pulses supplied from sources A' and B' respectivelycarry off any 'free charge remaining in the base zones throughseparating rectifiers 13, 14, `15, 16, 17 and 18. The collector of eachtransistor is connected to the base of the succeeding transistor byresistors 19, 20, 21, 22 and 23 conducting in both directions.

The circuit arrangement operates as follows:

It is first assumed that initially no transistor contains -free chargestorage. lf, now, the interrogating pulse A (FIG. 2) is received,currents ow via resistors 19, 2.1, 23 through the bases of theeven-numbered transistors 2., yIt, 6 and inject a free charge storageinto the base zones thereof. It, now, the interrogating pulse B (FIG. 2)is received, these transistors 2, l4, 6 will be so highly conductivethat, also owing to the preceding resistors 20, Z2

States Patent ice and the base-emitter threshold voltage of theseodd-numbered transistors 3, 5, a negligible current remains availableyfor the basses of the odd-numbered transistors.

If, now, free charge storage is imparted to the transistor 1, forexample by means of incident light or by supplying current to its basefor a short period of time, a current I1 will pass through thistransistor at the instant at which the interrogating pulse A issupplied, so that a negligible current ows through `the base of thetransistor 2 and consequently this transistor 2 is not conductive at theinstant at which the interrogating pulse B is received. Since at the endof an interrogating pulse any free charge storage is immediately removedby the erasing pulses A or B respectively, no current will subsequentlyflow through the transistor 1, so that each time subsequent to the rstpulse B free charge storage isl produced in the transistor 2 and acorresponding collector current flows in this transistor. Thus, thecollector current of the transistor Z is shown as a function of time byI2 in FIG. 2. Since this transistor was non-conductive during the yfirstinterrogating pulse B, at this instant base current is supplied to thetransistor 3 through the resistor 20, so that this transistor passes thecurrent I3 at the next subsequent interrogating pulse A, and so on.

Thus, during the interrogating pulses A the transistors 1, 3, 5 becomeconductive in sequence, that is to say, the ffree charge storageinjected into the transistor 1 as information to the next odd-numberedtransistor at each succeeding interrogating pulse A. Likewise, theabsence of yfree charge storage of the even-numbered transistors isshifted to the next even-numbered transistor at each interrogating pulseB.

For satisfactory operation it is required that in the intenvals betweentwo interrogating pulses any free charge storage which may have beeninjected has not leaked away. To this end, the resistors used,particularly the sum of the collector and 4the base resistors must besuiciently large. In practice, good results were obtained with resistorsof 6009 at a repetition frequency of the interrogating pulses of kc./s.However, such large resistors can be used Without diiculty, ras has beendescribed hereinbefore.

What is claimed is:

l. A transistor memory system comprising at least two stages connectedin cascade arrangement, each stage including a transistor having anemitter, la collector and a base, said base having the property ofstoring a free charge in response to current passed therein, meansconnected to apply current to the base of a rst one of said transistorsto cause a free charge to be stored therein, means for applyinginterrogating pulses to the respective emitter-collector circuits ofsaid transistors,y said interro- -gating pulses being the sole means ofpotential supply for said emitter-collector circuits, load resistorsconnected respectively in the collector circuit of each transistor, andbi-directionally conducting coupling resistors each connectedrespectively between the base of each transistor and the collector ofthe transistor of the preceding stage, the value of each couplingresistor and its associated load resistor being sufficiently large toprevent a free charge stored in the base to which the coupling resistoris connected from leaking away during the time interval between twosuccessive interrogating pulses applied to the transistor containingsaid base, each coupling resistor operating to couple pulses to the nextone when an interrogating pulse is applied to the preceding stagedependent on the presence of free charge in the base of the transistorof the preceding stage.

2. A transistor memory system comprising a plurality of stages connectedin cascade arrangement, each stage including a transistor having anemitter, a collector and 3 a ba'se,-said base having the property ofstoring a free charge in response to cur-rent passed therein, meansconnected -to apply current to the base of a rst one of said transistorsIto cause a free charge to =be stored therein, rneans for applyinginterrogating pulses to the respective emitteracollector circuits ofsaid transistors, said interrogating pulses being supplied alternatelyin time to the oddand even-numbered stages respectively, said interrogating pulses being the sole means of potential supply -for saidemitter-collector circuits, load resistors connected respectively in thecollector circuit of each transistor, and bi-directionally conductingcoupling resistors each connected respectively between the base of eachtransistor and the collector of the transistor of the next precedingstage, each coupling resistor and its associated load resistor havingmagnitudes suilicient to prevent any free charge stored in the base towhich the coupling resistor is connected from leaking away during thetime interval kefeienees Cited in the file of this patent UNITED STATESPATENTS `2,594,336 Mohr Apr. 29, 1952 2,644,892 Gehman July 7, 19532,548,658 AMitchell V Aug. 19,- 1958 2,877,357 Pears-all et al Mar. 10-,1959 2,910,596 Carlson Oct. 27, 1959 FOREIGN PATENTS 733,638 eGreafritain T1/ July 13, 1955

